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1 isl54228 high-speed usb 2.0 (480mbps) dpst switch with overvoltage protection (ovp) isl54228 the intersil isl54228 is a single supply, dual spst (single pole/single throw) switch that is configured as a dpst. it can operate from a single 2.7v to 5.25v supply. the part was designed for sw itching or isolating a usb high-speed source or a usb high-speed an d full-speed source in portable ba ttery powered products. the 3.5 spst switches were specifically designed to pass usb full speed and usb high speed data signals. they have high bandwidth an d low capacitance to pass usb high speed data signal s with minimal distortion. the device has two logic control pins (oe and lp) to control the spst switches. the isl54228 has ovp detection circuitry on the com pins to open the spst switches when the voltage at these pins exceeds 3.8v or goes negative by -0.45v. it isolates fault voltages up to +5.25v or down to -5v from getting passed to the other-side of the switch, thereby protecting the usb down-stream transceiver. the isl54228 is available in 8 ld 1.2mmx1.4mm tqfn and 8 ld 2mmx2mm tdfn packages. it operates over a temperature range of -40c to +85c. features ? high-speed (480mbps) and full-speed (12mbps) signaling capability per usb 2.0 ? 1.8v logic compatible (2.7v to +3.6v supply) ?low power state ? power off protection ? com pins overvoltage detection and protection for +5.25v and -5v fault voltages ? -3db frequency . . . . . . . . . . . . . . . . . . 790mhz ? low on capacitance @ 240mhz . . . . . . . . . . 2pf ? low on-resistance . . . . . . . . . . . . . . . . . . 3.5 ? single supply operation (v dd ) . . . . 2.7v to 5.25v ? available in tqfn and tdfn packages ? pb-free (rohs compliant) ? compliant with usb 2.0 short circuit and overvoltage requirements without additional external components applications* (see page 15) ? mp3 and other personal media players ? cellular/mobile phones, pda?s ? digital cameras and camcorders ? usb switching typical application usb 2.0 hs eye pattern with switches in the signal path isl54228 usb transceiver high-speed usb connector com - com + gnd d+ d- vdd oe p vbus d- d+ gnd ovp det 500 lp logic control 3.3v time scale (0.2ns/div) voltage scale (0.1v/div) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. july 29, 2010 fn7628.0
isl54228 2 fn7628.0 july 29, 2010 pin configurations isl54228 (8 ld 1.2x1.4 tqfn) top view isl54228 (8 ld 2x2 tdfn) top view note: switches shown for oe = logic ?0?. 2 4 oe com - gnd com + d- 3 1 5 6 7 vdd 8 d+ lp ovp logic 4m 4m vdd oe com- com+ d+ lp 1 2 3 4 8 7 6 5 gnd d- pd ovp logic 4m 4m pin descriptions tqfn tdfn pin name description 4 1 lp low power input 5 2 d+ usb data port 6 3 com+ usb data port 74gndground connection 8 5 com- usb data port 1 6 d- usb data port 27oeswitch enable 3 8 vdd power supply - pd pd thermal pad. tie to ground or float truth table input output signal at com pins lp oe d-, d+ state 0v to 3.6v 0 0 off normal 0v to 3.6v 0 1 on normal 0v to 3.6v 1 0 off low power 0v to 3.6v 1 1 on normal overvoltage range 0 0 off ovp overvoltage range 0 1 off ovp overvoltage range 1 0 off neg ovp limited positive ovp no persistence checking low power overvoltage range 1 1 off ovp note: logic ?0? when 0.5v, logic ?1? when 1.4v with a 2.7v to 3.6v supply. isl54228
isl54228 3 fn7628.0 july 29, 2010 table 1. usb - ovp possible situat ions and trip point voltage codec supply switch supply (v dd ) coms shorted to protected trip point min max 2.7v to 3.3v 2.7v to 5.25v vbus yes 3.62v 3.95v 2.7v to 3.3v 2.7v to 5.25v -5v yes -0.6v -0.29v ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl54228iruz-t (note 1, 3) u6 -40 to +85 8 ld 1.2mmx1.4mm tqfn (tape and reel) l8.1.4x1.2 isl54228iruz-t7a (note 1, 3) u6 -40 to +85 8 ld 1.2mmx1.4mm tqfn (tape and reel) l8.1.4x1.2 isl54228irtz-t (note 1, 2) 228 -40 to +85 8 ld 2mmx2mm tdfn (tape and reel) l8.2x2c ISL54228IRTZ-T7A (note 1, 2) 228 -40 to +85 8 ld 2mmx2mm tdfn (tape and reel) l8.2x2c isl54228iruzeval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requ irements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl54228 . for more information on msl please see techbrief tb363 . isl54228
isl54228 4 fn7628.0 july 29, 2010 absolute maximum ratings thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v vdd to comx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5v comx to dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.6v input voltages d+, d- . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to 6.5v com+, com- . . . . . . . . . . . . . . . . . . . . . . . - 5v to 6.5v oe, lp . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v continuous current (com-/d-, com+/d+) . . . . . . . 40ma peak current (com-/d-, com+/d+) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . 100ma esd rating: human body model (tested per jesd22-a114-f). . . . >2kv machine model (tested per jesd22-a115-a) . . . . . . >150v charged device model (tested per jesd22-c101-d) . >2kv latch-up tested per jedec; clas s ii level a . . . . . at +85c thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tqfn package (note 6, 8) . . 210 165 8 ld tdfn package (notes 5, 7). . . 96 19 maximum junction temperature (plastic package). . +150c maximum storage temperature range. . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp normal operat ing conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c v dd supply voltage range . . . . . . . . . . . . . . 2.7v to 5.25v logic control input voltage . . . . . . . . . . . . . . . 0v to 5.25v analog signal range v dd = 2.7v to 5.25v . . . . . . . . . . . . . . . . . . . 0v to 3.6v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 6. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. for jc , the ?case temp? location is taken at the package top center. electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v lp = gnd, v oeh =1.4v, v oel = 0.5v, (note 9), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units analog switch characteristics on-resistance, r on (high-speed) v dd = 2.7v, oe = 1.4v, i dx = 17ma, v com+ or v com- = 0v to 400mv (see figure 2, note 14) 25 - 3.5 5 full - - 7 r on matching between channels, r on (high-speed) v dd = 2.7v, oe = 1.4v, i dx = 17ma, v com+ or v com- = voltage at max r on , (notes 13, 14) 25 - 0.2 0.45 full - - 0.55 r on flatness, r flat(on) (high-speed) v dd = 2.7v, oe = 1.4v, i dx = 17ma, v com+ or v com- = 0v to 400mv (notes 12, 14) 25 - 0.26 1 full - - 1.2 on-resistance, r on v dd = 3.3v, oe = 1.4v, i comx = 17ma, v com+ or v com- = 3.3v (see figure 2, note 14) +25 - 6.8 17 full - - 22 off leakage current, i dx(off) v dd = 5.25v, oe = 0v, v dx =0.3v, 3.3v, v comx = 3.3v, 0.3v 25 -20 1 20 na full - 30 - na on leakage current, i dx(on) v dd = 5.25v, oe = 5.25v, v dx = 0.3v, 3.3v, v comx = 0.3v, 3.3v 25 -9 - 9 a full -12 - 12 a power off leakage current, i com+ , i com- v dd = 0v, v com+ = 5.25v, v com- = 5.25v, oe = 0v 25 - - 11 a power off logic current, i oe v dd = 0v, oe = 5.25v 25 - - 22 a power off d+/d- current, i d+ , i d- v dd = 0v, oe = v dd , v d+ = v d- = 5.25v 25 - - 1 a isl54228
isl54228 5 fn7628.0 july 29, 2010 overvoltage protection detection positive fault-protection trip threshold, v pfp v dd = 2.7v to 5.25v, oe = v dd (see table 1 on page 3) 25 3.62 3.8 3.95 v negative fault-protection trip threshold, v nfp v dd = 2.7v to 5.25v, oe = v dd (see table 1 on page 3) 25 -0.6 -0.45 -0.29 v off persistence time fault protection response time negative ovp response: v dd = 2.7v, sel = 0v or v dd , oe = v dd , v dx = 0v to -5v, r l = 15k 25 - 102 - ns positive ovp response: v dd = 2.7v, sel = 0v or v dd , oe = v dd , v dx = 0v to 5.25v, r l = 15k 25 - 2 - s on persistence time fault protection recovery time v dd = 2.7v, oe = v dd , v dx = 0v to 5.25v or 0v to -5v, r l = 15k 25 - 45 - s dynamic characteristics turn- on t im e, t on v dd = 3.3v, vinput = 3v, r l = 50 , c l = 50pf (see figure 1) 25 - 160 - ns turn-off time, t off v dd = 3.3v, vinput = 3v, r l = 50 , c l = 50pf (see figure 1) 25 - 60 - ns skew, (t skewout - t skewin ) v dd = 3.3v, oe = 3.3v, r l = 45 , c l = 10pf, t r = t f = 500ps at 480mbps, (duty cycle = 50%) (see figure 5) 25 - 50 - ps rise/fall degradation (propagation delay), t pd v dd = 3.3v, oe = 3.3v, r l = 45 , c l = 10pf, ( see figure 5) 25 - 250 - ps crosstalk v dd = 3.3v, r l = 50 , f = 240mhz (see figure 4) 25 - -39 - db off-isolation v dd = 3.3v, oe = 0v, r l = 50 , f = 240mhz 25 - -23 - db -3db bandwidth signal = 0dbm, 0.2vdc offset, r l = 50 25 - 790 - mhz off capacitance, c off f = 1mhz, v dd = 3.3v, lp = 0v, oe = 0v (figure 3) 25 - 2.5 - pf com on capacitance, c (on) f = 1mhz, v dd = 3.3v, lp = 0v, oe = 3.3v (figure 3) 25 - 4 - pf com on capacitance, c (on) f = 240mhz, v dd = 3.3v, lp = 0v, oe = 3.3v 25 - 2 - pf power supply characteristics power supply range, v dd full 2.7 5.25 v positive supply current, i dd v dd = 5.25v, oe = 5.25v, lp = gnd 25 - 45 56 a full - - 59 a positive supply current, i dd v dd = 3.6v, oe = 3.6v, lp = gnd 25 - 23 30 a full - - 34 a positive supply current, i dd (low power state) v dd = 3.6v, oe = 0v, lp = v dd 25 - 5 6 a full - - 10 a positive supply current, i dd v dd = 4.3v, oe = 2.6v, lp = gnd 25 - 35 45 a full - - 50 a electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v lp = gnd, v oeh =1.4v, v oel = 0.5v, (note 9), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units isl54228
isl54228 6 fn7628.0 july 29, 2010 positive supply current, i dd v dd = 3.6v, oe = 1.4v, lp = gnd 25 - 25 32 a full - - 38 a digital input characteristics input voltage low, v oel , v lpl v dd = 2.7v to 3.6v full - - 0.5 v input voltage high, v oeh , v lph v dd = 2.7v to 3.6v full 1.4 -- v input voltage low, v oel , v lpl v dd = 3.7v to 4.2v full - - 0.7 v input voltage high, v oeh , v lph v dd = 3.7v to 4.2 full 1.7 -- v input voltage low, v oel , v lpl v dd = 4.3v to 5.25v full - - 0.8 v input voltage high, v oeh , v lph v dd = 4.3v to 5.25v full 2.0 -- v input current, i oel , i lpl v dd = 5.25v, oe = 0v, lp = 0v full - -8.2 - na input current, i oeh , i lph v dd = 5.25v, oe = 5.25v, lp = 5.25v, 4m pull-down full - 1.4 - a notes: 9. v logic = input voltage to perform proper function. 10. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. 12. flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 13. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value. 14. limits established by characterization and are not production tested. test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixt ure and stray capacitance. figure 1b. test circuit figure 1. switching times electrical specifications - 2.7v to 5.25v supply test conditions: v dd = +3.3v, gnd = 0v, v lp = gnd, v oeh =1.4v, v oel = 0.5v, (note 9), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units 50% t r < 20ns t f < 20ns t off 90% vdd 0v v input 0v t on logic input switch input switch output 90% v out v out v (input) r l r l r on + ----------------------- - = switch input vin v out r l c l dx comx 50 50pf gnd v dd c oe v input isl54228
isl54228 7 fn7628.0 july 29, 2010 figure 2. r on test circuit figure 3. capacitance test circuit figure 4. crosstalk test circuit test circuits and waveforms (continued) v dd c v dd comx dx gnd v hsdx v 1 r on = v 1 /17ma 17ma repeat test for all switches. oe v dd c gnd comx dx impedance analyzer 0v or repeat test for all switches. oe vdd analyzer v dd c com+ signal generator r l gnd d+ 50 nc d- com- signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. oe vin isl54228
isl54228 8 fn7628.0 july 29, 2010 figure 5a. measurement points figure 5b. test circuit figure 5. skew test test circuits and waveforms (continued) din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ c l com+ d- gnd v dd c d+ com- c l out- din+ din- |tro - tri| delay due to switch for rising input and rising output signals. |tfo - tfi| delay due to switch for fa lling input and falling output signals. |tskew_0| change in skew through the switch for output signals. |tskew_i| change in skew through the switch for input signals. 15.8 15.8 143 143 45 45 v dd oe isl54228
isl54228 9 fn7628.0 july 29, 2010 application block diagram detailed description the isl54228 device is a dual single pole/single throw (spst) analog switch configured as a dpst that operates from a single dc power supply in the range of 2.7v to 5.25v. it was designed for switchin g a usb high-speed source or full-speed source in portable battery powered products. it is offered in small tqfn and tdfn packages for use in mp3 players, cameras, pdas, cellphones, and other personal media players. the part consists of two 3.5 high speed spst switches. these switches have high bandwidth and low capacitance to pass usb high-speed (480mbps) differential data signals with minimal edge and phase distortion. they can also swing from 0v to 3.6v to pass usb full speed (12mbps) differential data signals with minimal distortion. the device has a single logic control pin (oe) to open and close the two spst switches. the part has an lp control pin to put the part in a low power state. the part contains special overvoltage protection (ovp) circuitry on the com+ and com- pins. this circuitry acts to open the spst switches when the part senses a voltage on the com pins that is >3.8v (typ) or < -0.45v (typ). it isolates voltages up to 5.25v and down to -5v from getting through to the other side of the switches (d-, d+) to protect the usb down-stream transceiver connected at the d+ and d- pins. the isl54228 was designed for mp3 players, cameras, cellphones, and other personal media player applications that need to switch a high-speed or full- speed transceiver source. a typical application block diagram of this functionality is previously shown. a detailed description of the spst switches is provided in the following section. high-speed (dx) spst switches the dx switches are bi-directional switches that can pass usb high-speed and usb full-speed signals when vdd is in the range of 2.7v to 5.25v. when powered with a 2.7v su pply, these switches have a nominal r on of 3.5 over the signal range of 0v to 400mv with a r on flatness of 0.26 . the r on matching between the switches over this signal range is only 0.2 , ensuring minimal impact by the switches to usb high speed signal transitions. as the signal level increases, the r on switch resistance increases. at a signal level of 3.3v, the switch resistance is nominally 9.8 . see figures 8, 9, 10, 11, 12, 13 in the ?typical performance curves? beginning on page 12. the dx switches were specifically designed to pass usb 2.0 high-speed (480mbps) differential signals in the range of 0v to 400mv. they have low capacitance and high bandwidth to pass the usb high-speed signals with minimum edge and phase distortion to meet usb 2.0 high speed signal quality specifications. see figure 14 in the ?typical performance curves? on page 13 for usb high-speed eye pattern taken with switch in the signal path. the dx switches can also pass usb full-speed signals (12mbps) in the range of 0v to 3.6v with minimal portable media device isl54228 usb transceiver high-speed usb connector com - com + gnd d+ d- vdd oe controller vbus d- d+ gnd or full-speed ovp det 4m lp logic 4m 500 3.3v control isl54228
isl54228 10 fn7628.0 july 29, 2010 distortion and meet all th e usb requirements for usb 2.0 full-speed signaling. see figure 15 in the ?typical performance curves? on page 14 for usb full-speed eye pattern taken with switch in the signal path. the switches are active (turned on) whenever the oe voltage is logic ?1? (high) and the lp voltage is logic ?x? (don?t care) and off when the oe voltage is logic ?0? (low) and the lp voltage is logic ?x? (don?t care). when the oe voltage is lo gic ?0? (low) and the lp voltage is logic ?1? (high) the part goes into low power mode. overvoltage protection (ovp) the maximum normal operating signal range for the dx switches is from 0v to 3.6v. for normal operation, the signal voltage should not be allowed to exceed these voltage levels or go below ground by more than -0.3v. however, in the event that a positive voltage >3.8v (typ) to 5.25v, such as the usb 5v v bus voltage, gets shorted to one or both of the com+ and com- pins or a negative voltage < -0.45v (typ) to -5v gets shorted to one or both of the com pins, the isl54228 has ovp circuitry to detect the overvoltage condition and open the spst switches to prevent damage to the usb down-stream transceiver connected at the signal pins (d-, d+). the ovp and power-off protection circuitry allows the com pins (com-, com+) to be driven up to 5.25v while the v dd supply voltage is in the range of 0v to 5.25v. in this condition, the part draws < 100a of i comx and i dd current and causes no stress to the ic. in addition, the spst switches are off and the fault voltage is isolated from the other side of the switch. external v dd series resistor to limit i dd current during negative ovp condition a 100 to 1k resistor in series with the vdd pin (see figure 6) is required to limit the i dd current draw from the system power supply rail during a negative ovp fault event. with a negative -5v fault voltage at both com pins, the graph in figure 7 shows the i dd current draw for different external resistor values for supply voltages of 5.25v, 3.6v, and 2.7v. note: with a 500 resistor, the current draw is limited to around 5ma. when the negative fault voltage is removed, the i dd current will return to it?s normal operation current of 25 a to 45 a . the series resistor also provides improved esd and latch-up immunity. during an overvoltage transient event (such as occurs during system level iec 61000 esd testing), substrate currents can be generated in the ic that can trigger parasitic scr structures to turn on, creating a low impedance path from the vdd power supply to ground. this will result in a significant amount of current flow in the ic, which can potentially create a latch-up state or permanently damage the ic. the external vdd resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. under normal operation, the low microamp i dd current of the ic produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance . isl54228 operation the following will discuss using the isl54228 shown in the ?application block diagram? on page 9. power the power supply connected at the vdd pin provides the dc bias voltage required by the isl54228 part for proper operation. the isl54228 can be operated with a v dd voltage in the range of 2.7v to 5.25v. for lowest power consumption you should use the lowest v dd supply. a 0.01f or 0.1f decoupling capacitor should be connected from the vdd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the vdd pin as possible. figure 6. vdd series resistor to limit idd current during negative ovp and for enhanced esd and latch-up immunity figure 7. negative ovp i dd current vs resistor value vs v supply oe d+ 100 to 1k com+ com- v supply gnd c protection resistor ovp logic d- lp i dd vdd -5v fault voltage alm int low to indicate ovp 0 5 10 15 20 25 100 200 300 400 500 600 700 800 900 1k resistor ( ) i dd (ma) v com+ = v com- = -5v 2.7v 3.6v 5.25v isl54228
isl54228 11 fn7628.0 july 29, 2010 in a typical application, v dd will be in the range of 2.8v to 4.3v and will be connected to the battery or ldo of the portable media device. logic control the state of the isl54228 device is determined by the voltage at the oe pin, lp pin, and the signal voltage at the com pins. refer to ?truth table? on page 2. the oe and lp pins are internally pulled low through a 4m resistor to ground and can be tri-stated or left floating. the isl54228 is designed to minimize i dd current consumption when the logic co ntrol voltage is lower than the v dd supply voltage. with v dd = 3.6v and the oe logic pin is at 1.4v, the part typically draws only 25a. with v dd = 4.3v and the oe logic pin is at 2.6v, the part typically draws only 35a. driving the logic pin to the v dd supply rail minimizes power consumption. the oe and lp pin can be driven with a voltage higher than the v dd supply voltage. it can be driven up to 5.25v with a v dd supply in the range of 2.7v to 5.25v. low power mode if the oe pin = logic ?0?, and the lp pin = logic ?1? the switches will turn off (hig h impedance) and the part will be put in a low power mo de. in this mode, the part draws only 10a (max) of current across the operating temperature range. normal operation mode with a signal level in the range of 0v to 3.6v and with the lp pin = logic ?0? the swit ches will be on when the oe pin = logic ?1? and will be off (high impedance) when the oe pin = logic ?0?. usb 2.0 v bus short requirements the usb specification in section 7.1.1 states a usb device must be able to withstand a v bus short (4.4v to 5.25v) or a -1v short to the d+ or d- signal lines when the device is either powered off or powered on for at least 24 hours. the isl54228 part has special power-off protection and ovp detection circuitry to meet these short circuit requirements. this circuitry allows the isl54228 to provide protection to the usb down-stream transceiver connected at its signal pins (d-, d+) to meet the usb specification short circuit requirements. the power-off protection and ovp circuitry allows the com pins (com-, com+) to be driven up to 5.25v or down to -5v while the v dd supply voltage is in the range of 0v to 5.25v. in these overvoltage conditions, the part draws < 55a of current into the com pins and causes no stress/damage to the ic. in addition, all switches are off and the shorted v bus voltage will be isolated from getting through to the other side of the switch channels, thereby protecting the usb transceiver. table 2. logic control voltage levels v dd supply range logic = ?0? (low) logic = ?1? (high) oe lp oe lp 2.7v to 3.6v 0.5v or floating 0.5v or floating 1.4v 1.4v 3.7v to 4.2v 0.7v or floating 0.7v or floating 1.7v 1.7v 4.3v to 5.25v 0.8v or floating 0.8v or floating 2.0v 2.0v isl54228
isl54228 12 fn7628.0 july 29, 2010 typical performance curves t a = +25c, unless ot herwise specified figure 8. on-resistance vs supply voltage vs switch voltage figure 9. on-resistance vs supply voltage vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltage 2.9 3.0 3.1 3.2 3.3 3.4 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) 2.7v 3.3v i com = 17ma 3.6v 4.3v 5.25v 3.0v 3.3v 0 2 4 6 8 10 12 14 16 0 0.6 1.2 1.8 2.4 3.0 3.6 r on ( ) v com (v) 2.7v 3.0v 5.25v i com = 17ma 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) i com = 17ma +25c +85c -40c v+ = 2.7v 0 2 4 6 8 10 12 14 16 18 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 r on ( ) v com (v) +85c -40c i com = 17ma v+ = 2.7v +25c 2.0 2.5 3.0 3.5 4.0 0 0.1 0.2 0.3 0.4 r on ( ) v com (v) i com = 17ma +25c +85c -40c v+ = 3.3v 1 2 3 4 5 6 7 8 9 0 0.5 1.0 1.5 2.0 2.5 3.0 3.6 r on ( ) v com (v) +25c +85c -40c i com = 17ma v+ = 3.3v isl54228
isl54228 13 fn7628.0 july 29, 2010 figure 14. eye pattern: 480mbps with usb switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 3.3v isl54228
isl54228 14 fn7628.0 july 29, 2010 figure 15. eye pattern: 12mbps with usb switches in the signal path figure 16. frequency response figure 17. off-isolation typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v -4 -3 -2 -1 0 1 frequency (hz) normalized gain (db) 1m 10m 100m 1g v in = 0dbm, 0.86vdc bias r l = 50 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 frequency (mhz) normalized gain (db) 0.01 0.1 1 500 10 0.001 100 v in = 0dbm, 0.2vdc bias r l = 50 isl54228
isl54228 15 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7628.0 july 29, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl54228 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php figure 18. crosstalk die characteristics substrate and tdfn thermal pad potential (powered up): gnd transistor count: 1297 process: submicron cmos revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 7/29/10 fn7628.0 initial release. typical performance curves t a = +25c, unless ot herwise specified (continued) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 frequency (mhz) normalized gain (db) 0.01 0.1 1 500 10 0.001 100 v in = 0dbm, 0.2vdc bias r l = 50 isl54228
isl54228 16 fn7628.0 july 29, 2010 package outline drawing l8.2x2c 8 lead thin dual flat no-lead plastic package (tdfn) with e-pad rev 0, 07/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2.00 2.00 ( 6x0.50 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 0.800.050 exp.dap 0.25 1.450.050 exp.dap ( 8x0.25 ) 0.80 1.45 pin #1 index area b 0.10 m a c 0 . 75 ( 0 . 80 max) c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 6 index area pin 1 6 (4x) 0.15 a b 1 package outline 8 isl54228
isl54228 17 fn7628.0 july 29, 2010 isl54228 package outline drawing l8.1.4x1.2 8 lead quad flat no-lead plastic package rev 0, 4/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2x 0.10 1.20 index area 1.40 b a pin 1 c0.10 7x 0.30 0.05 0.40 bsc 4x 0.40 bsc 0.80 ref 0.30 0.40 c c 8 x 0.20 4 0.05 0.10 m ma b 0.60 pin 1 index area 6 8 1 5 4 2 pkg outline 4x 0.40 0.80 ref 0.60 7x 0.50 8 x 0.20 0.60 0.60 0.70 0.08 seating plane 0.10 c c c see detail "x" max. 0.50 0 . 2 ref 0-0.05 c

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